Most of the electronic devices nowadays rely on the integrated circuit (IC) chips, such as memory chips or display drivers, to operate. Attending with the development of IC technology, the IC chip has the shrinking trend. However, if the back end packaging technology cannot follow up the improvement of IC technology, the advantage of small IC chips will not be exhibited effectively.
Regarding the packaging technologies for IC chips, there has a metal bump processing for connecting the final metal pad of the IC chip. In order to enhance the density of connections, lithographic technology is usually used for forming the metal pads. After plating the metal bumps, it is usually demanded to apply an additional annealing process on the metal pads to further improve the characteristics and the hardness of the metal pads. However, because the thermal expansion coefficients of the metal pad, the metal bump, and the protection layer interposed between the metal bump and the metal pad are different, there might be cracks between the protection layer and the metal bump generated during the annealing process.
Please refer to FIG. 1, which shows a schematic view of a conventional chip to be packaged. As shown, the chip to be packaged PA100 includes an IC chip PA1 and a metal bump PA2. The IC chip PA1 has a metal pad PA11 and a protection layer PA12. The metal pad PA11 is exposed from the protection layer PA12. When applying annealing process to the chip to be packaged PA100, the crack event is usually formed at the junctions CR1 between the protection layer PA12 and metal pad PA11 as well as the metal bump PA2.
Please refer to FIG. 2, which shows a schematic view of another conventional chip to be packaged. As shown, the chip to be packaged PA100a includes an IC chip PA1a and a metal bump PA2a. The IC chip PA1a includes a metal pad PA11a, a protection layer PA12a, and a plurality of metal wires PA13a. The metal pad PA11a is exposed from the protection layer PA12a. The metal wires PA13a are adjacent to the metal pad PA11a and covered by the protection layer PA12a. Because of the small interval between the metal wires PA13a, air might be left between the metal wires PA13a to form the air chamber PA121a during the formation of the protection layer PA12a. When applying annealing process to the chip to be packaged PA100a, the crack event would be generated not only at the junctions between the protection layer PA12a and metal pad PA11a as well as the metal bump PA2a, but also at the junction CR2 between the protection layer PA12a and the metal wires PA13a due to the air chamber PA121a between the metal wires PA13a. 